1. Field of the Invention
The invention relates generally to gain control circuits of the type having a transconductance multiplier circuit biased by a bias circuit. More particularly, the invention concerns a variable gain amplifier ("VGA") with high beta immunity and supply voltage rejection suited for low voltage applications.
2. Description of the Prior Art
Gain control circuits are generally known and have widespread used in the electronic arts. With the increasing popularity of mobile and hand held computing and/or communicating devices, such as cell phones, laptop computers, and personal digital assistants, there is an increased need for gain control circuits which can withstand the supply voltage variations which commonly occur in battery operated devices. Additionally, in order to reduce power consumption, it is desirable for such gain control circuits to operate with low supply voltages, such as on the order of 3.5-5 volts.
Of particular usefulness are gain control circuits which allow the gain to be varied continuously. FIG. 1 shows a known circuit in the form of a bipolar Variable Gain Amplifier (VGA), which employs a Gilbert cell multiplier circuit 100. This circuit is known from the text: B. Gilbert, Analog IC Design, The Current-Mode Approach, Chapter 2 (United Kingdom 1990). The Gilbert multiplier circuit 100 (FIG. 1(a)) includes a pair of differentially coupled input transistors Q1A, Q1B and a pair of differentially coupled output transistors Q2A, Q2B. The collectors of the transistors are coupled to a supply 10. A differential input signal current is supplied to the bases of the two input transistors via the two input terminals 2 and 3. Each of the input transistors has a common base/collector and thereby function as diodes to convert the input current into a voltage at their respective bases/collectors. This voltage is then reconverted into a current at the output terminals 4 and 5 by the output transistors Q2A and Q2B. The emitters of the input transistors Q1A, Q1B are biased by a first bias current 2*I1 while the emitters of the output transistors Q2A, Q2B are biased by a second bias current 2*I2, both supplied by the bias circuit of FIG. 1(b).
The bias circuit of FIG. 1(b) includes a first current mirror consisting of the current mirror transistors Q3, Q4. The collector of the transistor Q3 serves as the input of the first current mirror 110, and is fed by a current source 101. The output of the current mirror 110 is coupled to the collector of the transistor Q4, and is related to the current provided by the current source 101, by a factor N, the current mirror ratio. Similarly, the second bias current is output by a second current mirror 120 consisting of the current mirror transistors Q5, Q6 fed by a second current source 102.
For this Gilbert cell, it is known from the above-mentioned text that the current gain between the common base/collector terminals of the input transistors Q1A, Q1B (the differential input current) and the collectors of the output transistors Q2A, Q2B (the differential output current), equals the ratio of the collector bias currents of the input and output transistors. Assuming infinite .beta.'s, this leads to the following current gain A.sub.i between the input and output terminals ##EQU1## where i.sub.out and i.sub.in, are the differential output and input currents, I.sub.c2 is the sum of the collector currents of the transistors Q2A, Q2B, and I.sub.c1 is the sum of the collector currents of the input transistors Q1A, Q1B. Similarly I.sub.e2 and I.sub.e1 are the sum of the emitter currents of the output and input transistors, respectively. Note that the right hand equality also holds for non-infinite .beta.'s. .beta. is defined as the common collector/base current amplification factor of a bipolar transistor.
The relative simplicity of the Gilbert cell in FIG. 1 and its predictable control characteristic have made the circuit a popular choice in bipolar intermediate frequency (IF) VGA circuits.
An important disadvantage surfaces, however, with real transistors that have non-infinite .beta.'s. Especially at high gain settings, the base currents of the output transistors Q2A, Q2B can result in a deviation from the gain predicted by Eq. 1. This is due to the fact that the base currents of the output transistors Q2A and Q2B are taken from the-input signal, which effectively lowers the actual signal current available at the collectors of the input transistors Q1A and Q1B. The total small-signal base current that is drained away from the input at each side of the circuit equals the sum of the base currents of the input transistors ("ib1") and the sum of the base output transistors ("ib2"). To first order, the sum of the base currents of the input transistors Q1A and Q1B is i.sub.in /.beta., while the sum for the output transistor Q2A and Q2B is A.sub.i i.sub.in /.beta.. Therefore, the total signal current directed away from the collectors of Q1A and Q1B is i.sub.in (1+A.sub.i)/.beta., and the total gain A.sub.i,.beta. becomes ##EQU2## By defining the desired gain setting A.sub.i,d ##EQU3## we can approximate Eq. 2 by ##EQU4## Assuming a current gain .beta. of 50 and a gain setting A.sub.i =A.sub.i,d of 10, the resulting gain A.sub.i,.beta. becomes 7.8, which amounts to a gain error of 22% between the actual gain and the desired gain setting A.sub.i,d.
It is an object of the invention to provide a gain control circuit with less error between the actual gain of the circuit and the ideal gain, as indicated by the ratio of the bias current of the output and input transistors.
It is another object of the invention to provide such a circuit while maintaining high supply voltage rejection.
It is yet another object of the invention to provide such a circuit suitable for low voltage operation.